Concepedia

Layout Optimization For Electrostatic Discharge

Layout Optimization for Electrostatic Discharge is a design methodology that systematically arranges physical components and interconnects within an integrated circuit to minimize susceptibility to electrostatic discharge events by reducing parasitic coupling paths and enhancing on-chip protection network efficiency.

52

Publications

1.6K

Citations

156

Authors

54

Institutions

Publications per year

2017–2026

9

Parents

Publications

52

Optimum geometry for strip cathodes or grids in MWPC for avalanche localization along the anode wires

E. Gatti, A. Longoni, H. Okuno et al. · Nuclear Instruments and Methods · 1979 · 131 citations

, , +5

NMOS protection circuitry

R.N. Rountree, Charles L. Hutchins · IEEE Transactions on Electron Devices · 1985 · 80 citations

, , +16

A New High Holding Voltage Dual-Direction SCR With Optimized Segmented Topology

Xiaozong Huang, Juin J. Liou, Zhiwei Liu et al. · IEEE Electron Device Letters · 2016 · 77 citations · Full text

, , +8

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Steven H. Voldman, V. Gross · Journal of Electrostatics · 1994 · 60 citations

, , +16

Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies

Steven H. Voldman, G. Gerosa · 2002 · 56 citations

, , +17

1–5 of 52

Authors

156

  1. MK
    Ming‐Dou Ker

    National Yang Ming Chiao Tung University, Taiwan

    13 publications · 297 citations

    11

    h-index

  2. JJ
    Juin J. Liou

    University of Central Florida, United States

    9 publications · 313 citations

    9

    h-index

  3. JA
    Javier A. Salcedo

    University of Central Florida, United States

    3 publications · 106 citations

    3

    h-index

  4. AW
    Albert Wang

    University of California, Riverside, United States

    3 publications · 77 citations

    3

    h-index

  5. WC
    Wenyi Chen

    National Yang Ming Chiao Tung University, Taiwan

    3 publications · 67 citations

    3

    h-index

1–5 of 156

Institutions

54

  1. National Yang Ming Chiao Tung University

    Hsinchu, Taiwan

    12 h-index

    34 publications

    813 citations

  2. I-Shou University

    Kaohsiung City, Taiwan

    8 h-index

    8 publications

    195 citations

  3. University of Central Florida

    Orlando, United States

    7 h-index

    12 publications

    404 citations

  4. Industrial Technology Research Institute

    Hsinchu, Taiwan

    5 h-index

    6 publications

    164 citations

  5. IBM (United States)

    Armonk, United States

    4 h-index

    12 publications

    375 citations

  6. Texas Instruments (United States)

    Dallas, United States

    4 h-index

    6 publications

    261 citations

  7. Zhejiang University

    Hangzhou, China

    3 h-index

    15 publications

    423 citations

  8. University of California, Riverside

    Riverside, United States

    3 h-index

    17 publications

    441 citations

1–8 of 54

Venues

  1. IEEE Transactions on Electron Devices

    14 publications · 366 citations

    12

    h-index

  2. IEEE Electron Device Letters

    5 publications · 202 citations

    5

    h-index

  3. 4

    h-index

  4. 3

    h-index

  5. IEEE Journal of Solid-State Circuits

    2 publications · 38 citations

    2

    h-index

1–5