Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package

K. Johguchi, Takeo Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, T. Sakurai, Ken Takeuchi

IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 16 citations · 14 references

Concepts

Abstract

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .

References

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