Masaya Kawano - Concepedia

Author

Masaya Kawano

Agency for Science, Technology and Research

Also Known As

M Kawano, Masaya KAWANO, Masaya Kawano

Publications

651

Citations

H-Index

Concepts

All Affiliations

Agency for Science, Technology and Research Institute of Microelectronics NEC (Japan)Renesas Electronics (Japan)Oki Electric Industry (Japan)

About

Masaya Kawano is an author at Agency for Science, Technology and Research specializing in engineering, microelectronics, and electronic packaging.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	13	476
2	Computer Engineering	8	8	295
3	Applied Physics	5	5	187
4	Natural Sciences	1	1	20
5	Biochemistry	1	1	20

Masaya Kawano

Publications

552

Citations

H-Index

Page 1

	Year	Citations
Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer Masaya Kawano, Nobuaki Takahashi, Yoichiro Kurita, IEEE Transactions on Electron Devices Advanced Packaging3D Ic ArchitectureElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)	2008	75
A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology Yoichiro Kurita, S. Matsui, Nobuaki Takahashi, EngineeringEmerging Memory TechnologyComputer ArchitectureInterconnect (Integrated Circuits)Multi-channel Memory Architecture	2007	74
Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages Lin Ji, Fa Xing, Hong Ji, IEEE Transactions on Components Packaging and Manufacturing Technology Materials EngineeringMaterials ScienceElectrical EngineeringWafer-to-wafer Hybrid BondingEngineering	2020	59
Dielectric Materials Characterization for Hybrid Bonding Vivek Chidambaram, Prayudi Lianto, Xiangyu Wang, DielectricsEngineeringPecvd Teos Sio2Shear StrengthHybrid Materials	2021	59
System in wafer-level package technology with RDL-first process Norikazu Motohashi, Takehiro Kimura, Kazuyuki MINEO,	2011	56
Fan-Out Wafer-Level Packaging with highly flexible design capabilities Yoichiro Kurita, Takehiro Kimura, K. Shibuya, EngineeringComputer ArchitectureFlexible Design CapabilitiesIntegrated CircuitsRefrigeration	2010	51
Bonding integrity enhancement in wafer to wafer fine pitch hybrid bonding by advanced numerical modelling Lin Ji, Fa Xing, Hong Ji, Materials ScienceMaterials Engineering3D Ic ArchitectureBonding ProcessEngineering	2020	33
Development of 3D-Packaging Process Technology for Stacked Memory Chips T. Mitsuhashi, Y. Egawa, Osamu Kato, MRS Proceedings 3D Ic ArchitectureChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Stacked Memory Chips	2006	26
Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling Fa Xing, Masaya Kawano, Mian Zhi Ding, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringPackage WarpageLow WarpageTfi TechnologyInterconnect (Integrated Circuits)	2017	22
Low-cost TSV process using electroless Ni plating for 3D stacked DRAM Masaya Kawano, Nobuaki Takahashi, Masahiro Komuro, EngineeringNi TsvsLow-cost Tsv ProcessIntegrated CircuitsInterconnect (Integrated Circuits)	2010	20

Page 1