A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Abstract

A general-purpose 3D-LSI platform technology for a high-capacity stacked memory integrated on a logic device was developed for high-performance, power-efficient, and scalable computing. SMAFTI technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was introduced for interconnecting the 3D stacked memory and the logic device. A DRAM-compatible manufacturing process was realized through the use of a "via-first" process and highly doped poly-Si through-silicon-vias (TSVs) for vertical traces inside memory dice. A multilayer ultra-thin die stacking process using micro-bump interconnection technology was developed, and Sn-Ag/Cu pillar bumps and Au/Ni backside bumps for memory dice were used for this technology. The vertical integration of stacked DRAM with TSVs and a logic device in a BGA package has been successfully achieved, and actual device operation has been demonstrated for the first time as a 3D-LSI with the DRAM introducing TSVs on the logic device.