Masahiro Komuro

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita et al. · IEEE Journal of Solid-State Circuits · 1996 · 87 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

M. Kawano, Shiro Uchiyama, Y. Egawa et al. · 2006 · 86 citations

Engineering, Computer Engineering, Electrical Engineering +17

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

Masaya Kawano, Nobuaki Takahashi, Yoichiro Kurita et al. · IEEE Transactions on Electron Devices · 2008 · 75 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · 2007 · 74 citations

Engineering, Computer Engineering, High-performance Computing +17

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · IEEE Transactions on Advanced Packaging · 2009 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +17