Shiro Uchiyama

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

M. Kawano, Shiro Uchiyama, Y. Egawa et al. · 2006 · 86 citations

Engineering, Gbit Dram, Computer Architecture +17

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · 2007 · 74 citations

Engineering, Emerging Memory Technology, Computer Architecture +21

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

K. Saino, S. Horiba, Shiro Uchiyama et al. · 2002 · 71 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +12

A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

Satoshi Takaya, Makoto Nagata, Atsushi Sakai et al. · 2013 · 46 citations

Engineering, Device Integration, Memory Chips +27

Development of 3D-Packaging Process Technology for Stacked Memory Chips

T. Mitsuhashi, Y. Egawa, Osamu Kato et al. · MRS Proceedings · 2006 · 26 citations

3D Ic Architecture, Chip-scale Package, Engineering +8