T. Mitsuhashi

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

M. Kawano, Shiro Uchiyama, Y. Egawa et al. · 2006 · 86 citations

Engineering, Gbit Dram, Computer Architecture +17

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · 2007 · 74 citations

Engineering, Emerging Memory Technology, Computer Architecture +21

A diagonal interconnect architecture and its application to RISC core design

M. Igarashi, T. Mitsuhashi, Alexandre Lê et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005 · 44 citations

Hardware Security, Electrical Engineering, Risc Core Design +15

Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies

Mayu Aoki, F. Furuta, Kazuyuki Hozawa et al. · 2013 · 31 citations

Engineering, Device Integration, Integrated Circuits +22

Development of 3D-Packaging Process Technology for Stacked Memory Chips

T. Mitsuhashi, Y. Egawa, Osamu Kato et al. · MRS Proceedings · 2006 · 26 citations

3D Ic Architecture, Chip-scale Package, Engineering +8