Development of 3D-Packaging Process Technology for Stacked Memory Chips - Concepedia

Concepedia

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Development of 3D-Packaging Process Technology for Stacked Memory Chips

26

Citations

1

References

2006

Year

T. Mitsuhashi, Y. Egawa, Osamu Kato, Yoshihiro Saeki, Hidekazu Kikuchi, Shiro Uchiyama, Kayoko Shibata, Junji Yamada, M. Ishino, Hiroaki Ikeda,

MRS Proceedings

3D Ic ArchitectureChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Stacked Memory ChipsComputer EngineeringComputer Architecture3D PrintingElectronic PackagingMicroelectronics3D Integration

References

	Year	Citations

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