MRS Proceedings · 2006 · 26 citations · 1 references
EngineeringComputer EngineeringComputer SystemsMicrofabricationPackaging DesignSemiconductor DevicesChip PackagingMemory DevicesMemory Hierarchy DesignMemory Subsystem DesignPackaging Engineering3D Integrated Circuits3D Stacked MemoryDevice PackagingThree-dimensional IntegrationWafer-level Packaging
1
Process integration of 3D chip stack with vertical interconnection
Kenji Takahashi, Yuichi Taguchi, M. Tomisaka et al. · 2004 · 84 citations
Engineering, Electrical Engineering, Materials Engineering +17