Hidekazu Kikuchi

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

M. Kawano, Shiro Uchiyama, Y. Egawa et al. · 2006 · 86 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · 2007 · 74 citations

Engineering, Computer Engineering, High-performance Computing +17

A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC

Masaki Sakakibara, Koji Ogawa, Shin Sakai et al. · 2018 · 69 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 6.9-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC

Masaki Sakakibara, Koji Ogawa, Shin Sakai et al. · IEEE Journal of Solid-State Circuits · 2018 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka et al. · 2011 · 32 citations

Engineering, Materials Engineering, Materials Science +17