A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

TLDR

The authors employ highly‑doped poly‑Si TSVs and wafer‑level SMAFTI packaging, along with a novel fine‑pitch, low‑cost feedthrough interposer bump and wiring structure, to interconnect stacked DRAM chips. The resulting 3D packaging yields 4‑Gbit DRAM with fast poly‑Si filling and supports up to 3 Gbps per pin, as shown by simulation.

Abstract

A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability