M. Ishino

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

M. Kawano, Shiro Uchiyama, Y. Egawa et al. · 2006 · 86 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita, S. Matsui, Nobuaki Takahashi et al. · 2007 · 74 citations

Engineering, Computer Engineering, High-performance Computing +17

Development of 3D-Packaging Process Technology for Stacked Memory Chips

T. Mitsuhashi, Y. Egawa, Osamu Kato et al. · MRS Proceedings · 2006 · 26 citations

Engineering, Computer Engineering, Computer Systems +13

Trends and opportunities of system-in-a-package and three-dimensional integration

Manabu Bonkohara, Kenji Takahashi, M. Ishino · Electronics and Communications in Japan (Part II Electronics) · 2005 · 21 citations

Engineering, Electrical Engineering, Materials Science +13

Microcarrier for LSI chip used in the HITAC M-880 processor group

Takashi Inoue, H. Matsuyama, E. Matsuzaki et al. · IEEE Transactions on Components Hybrids and Manufacturing Technology · 1992 · 10 citations

Engineering, Electrical Engineering, Materials Engineering +17