K. Saino

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

K. Saino, S. Horiba, Shiro Uchiyama et al. · 2002 · 71 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +12

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

C. Ortolland, S. Sahhaf, V. Srividya et al. · 2010 · 13 citations

Low-power Electronics, Vth Adjust, Electrical Engineering +10

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Y. Takai, Masafumi Fujita, K. Nagata et al. · IEEE Journal of Solid-State Circuits · 2000 · 12 citations

Hardware Security, 1-Gb Double-data-rate Sdram, Vlsi Design +15

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

K. Saino, K. Okonogi, S. Horiba et al. · 2002 · 10 citations

Non-volatile Memory, Electrical Engineering, Trench Sidewall Stress +12