Ken Takeuchi - Concepedia

Author

Ken Takeuchi

Also Known As

K Takeuchi, K. Takeuchi, Keita Takeuchi, Ken TAKEUCHI, Ken Takeuchi, Kenneth J. Takeuchi, Kento Takenaka, Takeuchi Ken, Takeuchi, Ken, Takeuchi, Kenneth J.; Takeuchi, Esther S.; Marschilok, Amy C.

454

Publications

Citations

H-Index

Concepts

All Affiliations

Chuo University The University of Tokyo Tokyo University of Information Sciences Toshiba (Japan)National Institute of Advanced Industrial Science and Technology

About

Ken Takeuchi is an author at Chuo University specializing in engineering, electrical engineering, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	28	81	3.1K
2	Computer Engineering	27	77	2.1K
3	Applied Physics	13	16	1.4K
4	Computer Science	13	16	435
5	Data Science	1	1	22

Ken Takeuchi

Publications

3.3K

Citations

H-Index

Page 1

	Year	Citations
Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays Tsuyoshi Sekitani, Tomoyuki Yokota, Ute Zschieschang, Science Non-volatile MemoryElectrical EngineeringEngineeringElectronic MaterialsFlexible Electronics	2009	955
A multipage cell architecture for high-speed programming multilevel NAND flash memories Ken Takeuchi, Tomoharu Tanaka, Tôru Tanzawa IEEE Journal of Solid-State Circuits Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringIc Error Rate	1998	90
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs) Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi IEEE Journal of Solid-State Circuits Non-volatile MemoryError-prediction LdpcEngineeringStorage PerformanceComputer Architecture	2013	78
Circuit techniques for a 1.8-V-only NAND flash memory Tôru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringCharge-pump CircuitEngineeringFlash Memory	2002	73
A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringVlsi DesignEmerging Memory TechnologyComputer Architecture	2007	70
A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringEngineeringNanoelectronicsFlash Memory	1996	70
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Non-volatile MemoryEngineeringVlsi DesignEmerging Memory TechnologyComputer Architecture	2012	65
Data-Retention Characteristics Comparison of 2D and 3D TLC NAND Flash Memories Kyoji Mizoguchi, Tomonori Takahashi, S. Aritome, Data Center SsdElectrical EngineeringNon-volatile MemoryEngineeringNanoelectronics	2017	63
Control of threshold voltage in low-voltage organic complementary inverter circuits with floating gate structures Tomoyuki Yokota, Takashi Nakagawa, Tsuyoshi Sekitani, Applied Physics Letters N-channel Organic TransistorsOrganic Material ChemistryElectrical EngineeringElectronic DevicesEngineering	2011	55
A compact on-chip ECC for low cost flash memories Tôru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, IEEE Journal of Solid-State Circuits Hardware SecurityNon-volatile MemoryElectrical EngineeringCompact On-chip ErrorConventional Ecc	1997	54

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