A multipage cell architecture for high-speed programming multilevel NAND flash memories

Abstract

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V/sub th/ of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 /spl mu/s/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized.