2005 · 20 citations · 8 references
EngineeringElectrical EngineeringFault ToleranceMicroelectronicsSemiconductor DevicesDesign For TestabilityDevice CharacterizationDevice ReliabilityElectrical System TestingFailure Mode AnalysisSemiconductor ReliabilityBreakdown MechanismsDielectric BreakdownElectrical TestabilityFailure Mode AssessmentFailure Mode ClassificationFailure Mode DetectionPackaging Reliability TestingRobustness Testing Methodology
Of 30 bipolar, BiCMOS, and CMOS products socketed CDM classified, 27 had /spl ges/500 V withstand voltages and experienced no real-world CDM fallout. Two of three products with <500 V withstand voltages had numerous manufacturing-induced CDM failures until they were analyzed and redesigned. Analysis of these two products showed that both socketed and non-socketed CDM testing replicated the initial dielectric breakdown failure mechanisms at the same failure sites identified on real-world CDM failures. However, socketed CDM testing consistently induced more severe damage than non-socketed CDM testing. On one product, this resulted in a completely different failure mode than that on the socketed CDM and real-world failures. Based on this work, a combined socketed and non-socketed CDM test approach is proposed for classifying/evaluating new products and driving CDM robustness improvements.
8
Latent gate oxide defects caused by CDM-ESD
Joachim C. Reiner · 1995 · 29 citations
Engineering, Computer Engineering, Electrical Engineering +17