Advanced CMOS protection device trigger mechanisms during CDM

Abstract

The Charged Device Model (CDM) is now considered to be an important stress model for defining ESD reliability of IC chips. This paper examines the CDM performance for three different advanced protection devices in a 0.35 /spl mu/m LDD CMOS technology. Through failure analysis and device simulations, the behavior of these protection devices during the CDM event is investigated. The results will enable devices to be designed for improved CDM protection levels.