International Journal of Circuit Theory and Applications · 2023 · 10 citations · 27 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesDevice ReliabilityMemory DevicesMemory Subsystem DesignRadiation HardeningRadiation-resistant MaterialsSemiconductor ReliabilityAerospace ApplicationsRadiation-hard DevicesRadiation-hard ElectronicsRadiation-hardened Integrated CircuitsRadiation-hardened MemoryRadiation-hardened Memory DevicesStatic Noise MarginStatic Random-access Memory Design
Summary In this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications.
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