IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2018 · 173 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignLow-power Digital Circuit DesignPower ManagementPower OptimizationRadiation HardeningDevice OptimizationMemory Circuit DesignPower ConsumptionPower Consumption OptimizationRadiation-hardened Integrated CircuitsRadiation-hardened MemoryRadiation-hardened Memory DevicesRadiation-hardening Techniques
In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event-multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.
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