T. Calin - Concepedia

Concepedia

Author

T. Calin

Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Also Known As

CALIN, T., Calin, T., T. Calin

23

Publications

1.4K

Citations

8

H-Index

15

Concepts

All Affiliations

Techniques of Informatics and Microelectronics for Integrated Systems Architecture European Organization for Nuclear Research The Aerospace Corporation

TC

About

T. Calin is an author at Techniques of Informatics and Microelectronics for Integrated Systems Architecture specializing in microelectronics, hardware security, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	5	5	1.3K
2	Computer Engineering	5	5	1.3K
3	Applied Physics	2	2	69
4	Natural Sciences	1	1	65
5	Biomedical Engineering	1	1	48

T. Calin

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8

Publications

1.4K

Citations

8

H-Index

	Year	Citations
Upset hardened memory design for submicron CMOS technology T. Calin, M. Nicolaidis, Raoul Velazco IEEE Transactions on Nuclear Science Hardware SecurityElectrical EngineeringHardened Memory DesignEngineeringVlsi Design	1996	1.1K
Deep submicron CMOS technologies for the LHC experiments P. Jarron, G. Anelli, T. Calin, Nuclear Physics B - Proceedings Supplements Collider PhysicPhysicsNatural SciencesParticle PhysicsLhc Experiments	1999	65
Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology F. Faccio, K. Kloukinas, A. Marchioro, IEEE Transactions on Nuclear Science	1999	58
SEU-hardened storage cell validation using a pulsed laser R. Velazco, T. Calin, M. Nicolaidis, IEEE Transactions on Nuclear Science Hardware SecurityElectrical EngineeringEngineeringHardware ReliabilityLaser-induced Breakdown	1996	48
Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments T. Calin, Fabian Vargas, M. Nicolaidis Hardware SecurityElectrical EngineeringCmos Static RamsEngineeringVlsi Design	2002	29
A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results T. Calin, Fabian Vargas, M. Nicolaidis, IEEE Transactions on Nuclear Science Hardware SecurityReliable Seu-tolerant SramElectrical EngineeringNon-volatile MemoryEngineering	1995	24
Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology G.F. Marchioro, P. Moreira, E. Noah, HAL (Le Centre pour la Communication Scientifique Directe)	1998	22
Topology-related upset mechanisms in design hardened storage cells T. Calin, Raoul Velazco, M. Nicolaidis, Hardware SecurityDefect ToleranceElectrical EngineeringTopology-related Upset MechanismsEngineering	2002	21

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