Improvement of Electron Transport Property and on-Resistance in Normally-OFF Al₂O₃/AlGaN/GaN MOS-HEMTs Using Post-Etch Surface Treatment

Abstract

Post-etch surface treatment technique was developed for normally-OFF recess-gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs). By removing the residues and smoothing surface morphology after plasma etch, the diffusion-controlled interface oxidation (DCIO) and wet etch in MOS-HEMTs lead to a decrease in interface traps from 1.04 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> to 6.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> with a filling voltage of 12 V. Field-effect mobility extracted in the linear region is 48 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s for MOS-HEMTs with an optimized post-etch surface treatment process, 33% larger than the case with the conventional chemical clean process. Due to the increased electron mobility and decreased sheet resistance beneath the gate by over 30%, normally-OFF MOS-HEMTs with DCIO and wet etch exhibit a remarkable increase in output current by about 29% and an increase in peak transconductance from 35 to 41 mS/mm. The optimized post-etch surface treatment method also enhances blocking voltage from 120 to 230 V by suppressing the leakage current resulting from gate soft breakdown. Dynamic characterization shows that the normalized ON-resistance is increased by double with drain stress up to 80 V, and various post-etch surface treatment processes have little effect on current collapse. Two types of threshold voltage shifts caused by interface trapping and border trapping are observed in the normally-OFF MOS-HEMTs, which keeps stable with an increase in temperature up to 125 °C.