Investigation and Failure Mode of Asymmetric and Double Trench SiC mosfets Under Avalanche Conditions

Abstract

In this article, commercially 1200-V asymmetric and double trench silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (mosfets) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with mosfet avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that two failure mechanisms are identified, i.e., thermal runaway and gate oxide rupture. For asymmetric trench SiC mosfets, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC mosfets is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of dc parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.