EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingIntegrated Circuit DesignPhysical DesignVery-large-scale Integration LayoutDevice IsolationFabricationFabrication TechniquesIsolationIsolation EnhancementIsolation Mechanisms
Scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity are discussed quantitatively. We review how LOCOS and STI isolation are being improved to meet these requirements. Independent of fabrication techniques, we see that a necessary consequence of achieving the desired narrow isolation and abrupt transitions is a discrete edge parasitic. We show that the edge parasitic can be distinguished from the planar channel and can be characterized separately. Edge device sensitivities are investigated with experiment and simulation to show that design and process control of the discrete edge parasitic will be a significant thrust of device engineering for future isolation technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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The current-carrying corner inherent to trench isolation
A. Bryant, Wilfried Haensch, J. Mandelman et al. · IEEE Electron Device Letters · 1993 · 35 citations
Engineering, Computer Engineering, Electrical Engineering +15
Reverse L-shape sealed poly-buffer LOCOS technology
J.M. Sung, Chun‐An Lu, L.B. Fritzinger et al. · IEEE Electron Device Letters · 1990 · 24 citations
Characterization of polysilicon-encapsulated local oxidation
S. Roth, W. Ray, C. Mazuré et al. · IEEE Transactions on Electron Devices · 1992 · 16 citations