In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability

Abstract

For advanced CMOS technology nodes, the global/local variability is challenging to handle during conception. In-situ monitor (ISM) is suitable to minimize all margins related to manufacturing variations and operating conditions. After the introducing the ISM concept, a complete insertion scheme is presented in industrial flow. A dedicated test chip is developed where ISMs are inserted in a digital block. An intensive measurement campaign is performed, and results are deeply investigated. Various effects like temperature, voltage, and ISM time window are analyzed both at IP level (Fmax/Vmin) and at gate cell level (critical path) on large sampling and compared to different hierarchal tools (spice, timing analysis, activity by power estimation tool).