Concepedia

Gate-level Modeling

Gate-Level Modeling is a hardware modeling methodology that represents digital systems as interconnections of logic gates, distinguished by its focus on implementing Boolean functions at the transistor-abstracted level for synthesis, simulation, and verification purposes.

462

Publications

16.9K

Citations

1.2K

Authors

350

Institutions

Publications per year

2017–2026

48

Parents

Publications

462

Power analysis of embedded software: a first step towards software power minimization

Vivek Tiwari, Sharad Malik, A. Wolfe · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1994 · 997 citations

, , +17

Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

Ronald L. Wadsack · Bell System Technical Journal · 1978 · 613 citations

, , +17

RT-level ITC'99 benchmarks and first ATPG results

Fulvio Corno, M. Sonza Reorda, Giovanni Squillero · IEEE Design & Test of Computers · 2000 · 535 citations

, , +17

MOTIS-An MOS timing simulator

B.R. Chawla, H.K. Gummel, P. Kozak · IEEE Transactions on Circuits and Systems · 1975 · 312 citations

, , +17

High-speed Booth encoded parallel multiplier design

Wen-Chang Yeh, Chein-Wei Jen · IEEE Transactions on Computers · 2000 · 277 citations

, , +15

1–5 of 462

Authors

1.2K

  1. SR
    S.M. Reddy

    University of Iowa, United States

    11 publications · 405 citations

    11

    h-index

  2. IP
    Irith Pomeranz

    University of Iowa, United States

    8 publications · 253 citations

    8

    h-index

  3. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    7 publications · 200 citations

    7

    h-index

  4. RU
    Raimund Ubar

    Tallinn University of Technology, Estonia

    7 publications · 84 citations

    7

    h-index

  5. JP
    John P. Hayes

    University of Michigan, United States

    7 publications · 344 citations

    7

    h-index

1–5 of 1.2K

Institutions

350

  1. University of Illinois Urbana-Champaign

    Urbana, United States

    15 h-index

    37 publications

    2K citations

  2. University of Michigan

    Ann Arbor, United States

    14 h-index

    48 publications

    2.3K citations

  3. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    13 h-index

    35 publications

    1.5K citations

  4. Politecnico di Torino

    Turin, Italy

    12 h-index

    32 publications

    2.8K citations

  5. University of Iowa

    Iowa City, United States

    12 h-index

    24 publications

    978 citations

  6. University of California San Diego

    San Diego, United States

    11 h-index

    25 publications

    610 citations

  7. Princeton University

    Princeton, United States

    10 h-index

    19 publications

    3.5K citations

  8. The University of Texas at Austin

    Austin, United States

    10 h-index

    18 publications

    402 citations

1–8 of 350

Venues

  1. 24

    h-index

  2. Design Automation Conference

    Conference · 16 publications · 509 citations

    14

    h-index

  3. IEEE Transactions on Computers

    13 publications · 1K citations

    11

    h-index

  4. 9

    h-index

  5. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 6 publications · 152 citations

    6

    h-index

1–5