On-chip Variation Analysis

On-Chip Variation Analysis is a timing analysis methodology that characterizes and quantifies the spatial and temporal variations in process, voltage, and temperature across a semiconductor die to enable accurate timing sign-off under real-world operating conditions.

267

Publications

11.6K

Citations

890

Authors

212

Institutions

Publications per year

2017–2026

24

Variants

Ocv Analysis

Authors

890

  1. SN
    Sani Nassif

    IBM Research - Austin, United States

    9 publications · 491 citations

    9

    h-index

  2. KB
    Keith Bowman

    Intel (United States), United States

    7 publications · 1K citations

    7

    h-index

  3. DS
    Dennis Sylvester

    University of Michigan, United States

    7 publications · 215 citations

    7

    h-index

  4. BN
    Borivoje Nikolić

    University of California, Berkeley, United States

    7 publications · 266 citations

    7

    h-index

  5. VD
    Vivek De

    Intel (United States), United States

    7 publications · 1K citations

    7

    h-index

1–5 of 890

Venues

  1. 9

    h-index

  2. 9

    h-index

  3. IEEE Journal of Solid-State Circuits

    8 publications · 1.7K citations

    8

    h-index

  4. 7

    h-index

  5. 7

    h-index

1–5