On-chip Variation Analysis
On-Chip Variation Analysis is a timing analysis methodology that characterizes and quantifies the spatial and temporal variations in process, voltage, and temperature across a semiconductor die to enable accurate timing sign-off under real-world operating conditions.
267
Publications
11.6K
Citations
890
Authors
212
Institutions
Publications per year
2017–2026
24
Variants
Ocv Analysis
267
FreePDK: An Open-Source Variation-Aware Design Kit
James E. Stine, Ivan D. Castellanos, Michael Wood et al. · 2007 · 429 citations
Genotyping microarray (gene chip) for the<i>ABCR</i>(<i>ABCA4</i>) gene
Kaie Jaakson, Jana Zernant, Maigi Külm et al. · Human Mutation · 2003 · 239 citations
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IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
15 h-index
47 publications
1.5K citations
Intel (United States)
Santa Clara, United States
15 h-index
63 publications
6.4K citations
IBM (United States)
Armonk, United States
14 h-index
71 publications
2.9K citations
University of California, Berkeley
Berkeley, United States
10 h-index
28 publications
1K citations
Carnegie Mellon University
Pittsburgh, United States
10 h-index
34 publications
1.7K citations
IBM Research - Austin
Austin, United States
10 h-index
13 publications
726 citations
The University of Texas at Austin
Austin, United States
8 h-index
16 publications
835 citations
Georgia Institute of Technology
Atlanta, United States
8 h-index
15 publications
2.2K citations
1–8 of 212
9 publications · 257 citations
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9 publications · 1.3K citations
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8 publications · 1.7K citations
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7 publications · 320 citations
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7 publications · 303 citations
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