Concepedia

Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages

Marc-Thomas Eisele, J. Berthold, R. Thewes, E. Wohlrab, D. Schmitt‐Landsiedel, W. Weber

2002 · 32 citations · 5 references

Abstract

Statistical intra-die variations of device parameters from a 0.5 /spl mu/m CMOS process are determined, finding good agreement with the (WL)/sup -1/2/ model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined.

References

5

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Engineering, Electrical Engineering, Materials Science +12

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Engineering, Electrical Engineering, Analog Electronics +16

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Engineering, Computer Engineering, Electrical Engineering +16

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Engineering, Computer Engineering, Electrical Engineering +17