D. Schmitt‐Landsiedel

Author

Also Known As

D Schmitt-Landsiedel, D. SCHMITT-LANDSIEDEL, D. Schmitt Landsiedel, D. Schmitt-Landsiedel, D. Schmitt‐Landsiedel, DORIS SCHMITT-LANDSIEDEL, Doris Schmitt-Landsiedel, Doris Schmitt‐Landsiedel, Schmitt-Landsiedel, Doris

362

Publications

6.5K

Citations

H-Index

214

Concepts

All Affiliations

Technical University of Munich Infineon Technologies (Germany)University of Notre Dame Siemens (Germany)Ludwig-Maximilians-Universität München

About

D. Schmitt‐Landsiedel is an author at Technical University of Munich specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	36	128	5.5K
2	Natural Sciences	11	13	430
3	Social Sciences	3	3	608
4	Education	1	1	21
5	Medicine	1	1	29

D. Schmitt‐Landsiedel

134

Publications

5.7K

Citations

H-Index

Page 1

	Year	Citations
Complementary tunneling transistor for low power application Pengzhan Wang, K. Hilsenbeck, T. Nirschl, Solid-State Electronics Low-power ElectronicsElectrical EngineeringEngineeringTunneling MicroscopyNanoelectronics	2004	510
Yield and speed optimization of a latch-type voltage sense amplifier Bernhard Wicht, T. Nirschl, D. Schmitt‐Landsiedel IEEE Journal of Solid-State Circuits Quantitative Yield AnalysisElectrical EngineeringEngineeringCircuit SystemData Converter	2004	482
A 128 x 128 cmos biosensor array for extracellular recording of neural activity B. Eversmann, M. Jenkner, Franz Hofmann, IEEE Journal of Solid-State Circuits Cmos Biosensor ArrayMedical ElectronicsEngineeringNeuromodulation TherapiesBiomedical Engineering	2003	377
A 128 × 128 CMOS bio-sensor array for extracellular recording of neural activity B. Eversmann, M. Jenkner, Christian Paulus, Medical ElectronicsEngineeringCmos Bio-sensor ArrayBiomedical EngineeringNeurochip	2003	217
A 0.5-v 1--μW successive approximation adc J. Sauerbrey, D. Schmitt‐Landsiedel, R. Thewes IEEE Journal of Solid-State Circuits Numerical AnalysisEngineeringData ConverterVoltage Boosting TechniquesAnalog Design	2003	209
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits Marc-Thomas Eisele, J. Berthold, D. Schmitt‐Landsiedel, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Path Delay VariationsElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	1997	160
Scaling properties and electromigration resistance of sputtered Ag metallization lines Matheus Hauder, J. Gstöttner, W. Hänsch, Applied Physics Letters EngineeringElectronic PackagingThin Film ProcessingMaterials EngineeringMaterials Science	2001	118
Scaling properties of the tunneling field effect transistor (TFET): Device and circuit T. Nirschl, St. Henzler, J. Fischer, Solid-State Electronics Device ModelingElectrical EngineeringEngineeringTunneling MicroscopyElectronic Engineering	2005	101
Majority Gate for Nanomagnetic Logic With Perpendicular Magnetic Anisotropy Stephan Breitkreutz, Josef Kiermaier, Irina Eichwald, IEEE Transactions on Magnetics Nanomagnetic LogicMagnetismSpintronicsElectrical EngineeringPerpendicular Magnetic Anisotropy	2012	88
A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology J. Sauerbrey, T. Tille, D. Schmitt‐Landsiedel, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringSwitched-opamp TechniqueEngineeringData Converter	2002	86

Page 1