J. Berthold

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

Marc-Thomas Eisele, J. Berthold, D. Schmitt‐Landsiedel et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1997 · 162 citations

Engineering, Computer Engineering, Electrical Engineering +17

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

K. von Arnim, E. Borinski, P. Seegebrecht et al. · IEEE Journal of Solid-State Circuits · 2005 · 56 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

C. Pacha, B. Martin, K. von Arnim et al. · 2004 · 53 citations

Engineering, Electrical Engineering, Microelectronics +16

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

K. von Arnim, C. Pacha, Karl Hofmann et al. · 2007 · 40 citations

Engineering, Computer Engineering, Electrical Engineering +17

Sleep transistor circuits for fine-grained power switch-off with short power-down times

Stephan Henzler, T. Nirschl, Stylianos Skiathitis et al. · 2005 · 36 citations

Engineering, Computer Engineering, Electrical Engineering +17