IEEE Electron Device Letters · 2004 · 56 citations · 11 references
Gate StackElectrical EngineeringEngineeringPhysicsNanoelectronicsBias Temperature InstabilityApplied PhysicsCondensed Matter PhysicsFermi-level PinningEffective Work FunctionThermodynamicsWork Function TuningSilicon On InsulatorMicroelectronicsHbox Tan/sio_2Beyond CmosSemiconductor Device
In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.
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Fermi level pinning at the polySi/metal oxide interface
Chris Hobbs, L.M. Fonseca, V. Dhandapani et al. · 2004 · 111 citations