Publication | Closed Access
Fermi level pinning at the polySi/metal oxide interface
111
Citations
1
References
2004
Year
Unknown Venue
EngineeringSilicon On InsulatorSemiconductor DeviceFermi Level PinningNanoelectronicsMaterials EngineeringElectrical EngineeringPolysi/metal Oxide InterfacePhysicsOxide ElectronicsBias Temperature InstabilityMicroelectronicsSolid-state PhysicFermi PinningStress-induced Leakage CurrentApplied PhysicsCondensed Matter PhysicsMosfet DevicesInterface Structure
We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.
| Year | Citations | |
|---|---|---|
Page 1
Page 1