A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)

Abstract

This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach