2005 · 167 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringTest DevelopmentBuilt-in Self-testDelay ModelingDesign For TestabilityDevice CharacterizationTiming AnalysisTiming ModelingBoundary ScanBoundary Scan ArchitectureBoundary Scan TestingDesign For ScanabilityFlip-flop DesignPath Delay AnalysisPath Delay ModelingTiming Characterization
1. Abstract This paper describes a novel flip-flop design which is used in performing internal path-delay test and measurement using scanpath technique:;. Also described is the design for a boundary-scan cell that enables inpUtlOUtpUt delays to be measured. The paper includes a real-life application example.
5