Path Delay Modeling
Path Delay Modeling is a computational method that precisely characterizes the propagation delay of signals along timing paths in digital circuits by accounting for process, voltage, temperature variations, and spatial correlations, thereby enabling accurate timing analysis and optimization during the timing closure process.
350
Publications
15K
Citations
746
Authors
254
Institutions
Publications per year
2017–2026
19
Parents
350
Model for Delay Faults Based Upon Paths
Gordon L. Smith · International Test Conference · 1985 · 710 citations
Measuring the gap between FPGAs and ASICs
Ian Kuon, Jonathan Rose · 2006 · 319 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 350
746
13
h-index
12
h-index
11
h-index
9
h-index
Southern Illinois University Carbondale, United States
7 publications · 123 citations
7
h-index
1–5 of 746
254
Intel (United States)
Santa Clara, United States
13 h-index
29 publications
662 citations
University of Iowa
Iowa City, United States
12 h-index
26 publications
974 citations
University of California, Berkeley
Berkeley, United States
12 h-index
32 publications
2.1K citations
University of California, Santa Barbara
Santa Barbara, United States
10 h-index
26 publications
974 citations
AT&T (United States)
Bedminster, United States
9 h-index
13 publications
404 citations
Motorola (United States)
Schaumburg, United States
9 h-index
28 publications
2.1K citations
Jet Propulsion Laboratory
Pasadena, United States
9 h-index
14 publications
641 citations
The University of Texas at Austin
Austin, United States
8 h-index
18 publications
854 citations
1–8 of 254
27 publications · 3K citations
19
h-index
13 publications · 512 citations
12
h-index
5 publications · 129 citations
5
h-index
5 publications · 300 citations
5
h-index
5 publications · 319 citations
5
h-index
1–5