Path Delay Modeling

Path Delay Modeling is a computational method that precisely characterizes the propagation delay of signals along timing paths in digital circuits by accounting for process, voltage, temperature variations, and spatial correlations, thereby enabling accurate timing analysis and optimization during the timing closure process.

350

Publications

15K

Citations

746

Authors

254

Institutions

Publications per year

2017–2026

19

Authors

746

  1. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    16 publications · 463 citations

    13

    h-index

  2. SR
    S.M. Reddy

    University of Iowa, United States

    14 publications · 509 citations

    12

    h-index

  3. IP
    Irith Pomeranz

    University of Iowa, United States

    13 publications · 399 citations

    11

    h-index

  4. KK
    Kurt Keutzer

    University of California, Berkeley, United States

    9 publications · 726 citations

    9

    h-index

  5. ST
    Spyros Tragoudas

    Southern Illinois University Carbondale, United States

    7 publications · 123 citations

    7

    h-index

1–5 of 746

Venues

  1. 19

    h-index

  2. 12

    h-index

  3. IEEE Journal of Solid-State Circuits

    5 publications · 129 citations

    5

    h-index

  4. 5

    h-index

  5. 5

    h-index

1–5