Timing Faults

Timing Fault is a type of fault model in digital circuit testing that belongs to the category of permanent faults and is distinguished by its characterization of delays in signal propagation that violate the circuit’s specified timing constraints, leading to incorrect circuit behavior under normal operating conditions.

691

Publications

25.9K

Citations

1.1K

Authors

302

Institutions

Publications per year

2017–2026

27

Authors

1.1K

  1. SR
    S.M. Reddy

    University of Iowa, United States

    48 publications · 2.4K citations

    28

    h-index

  2. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    45 publications · 1.8K citations

    27

    h-index

  3. IP
    Irith Pomeranz

    University of Iowa, United States

    42 publications · 1.2K citations

    20

    h-index

  4. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    33 publications · 1K citations

    18

    h-index

  5. AK
    A. Krstić

    University of California, Santa Barbara, United States

    17 publications · 569 citations

    16

    h-index

1–5 of 1.1K

Venues

  1. 33

    h-index

  2. 16

    h-index

  3. IEEE Transactions on Computers

    20 publications · 1K citations

    14

    h-index

  4. IEEE Design & Test of Computers

    13 publications · 857 citations

    12

    h-index

  5. Journal of Electronic Testing

    JETTA · 13 publications · 228 citations

    11

    h-index

1–5