Timing Faults
Timing Fault is a type of fault model in digital circuit testing that belongs to the category of permanent faults and is distinguished by its characterization of delays in signal propagation that violate the circuit’s specified timing constraints, leading to incorrect circuit behavior under normal operating conditions.
691
Publications
25.9K
Citations
1.1K
Authors
302
Institutions
Publications per year
2017–2026
27
Parents
691
Model for Delay Faults Based Upon Paths
Gordon L. Smith · International Test Conference · 1985 · 710 citations
Algorithms for scheduling imprecise computations
J.W.S. Liu, Kuo-Yi Lin, Wen-Chieh Shih et al. · Computer · 1991 · 528 citations
Clock recovery from random binary signals
John Alexander · Electronics Letters · 1975 · 309 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 691
1.1K
28
h-index
University of California, Santa Barbara, United States
45 publications · 1.8K citations
27
h-index
20
h-index
18
h-index
16
h-index
1–5 of 1.1K
302
University of Iowa
Iowa City, United States
28 h-index
83 publications
4.3K citations
University of California, Santa Barbara
Santa Barbara, United States
27 h-index
131 publications
4.2K citations
IBM (United States)
Armonk, United States
20 h-index
61 publications
3.9K citations
The University of Texas at Austin
Austin, United States
20 h-index
51 publications
1.9K citations
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Montpellier, France
19 h-index
96 publications
2.5K citations
Intel (United States)
Santa Clara, United States
19 h-index
100 publications
8.3K citations
AT&T (United States)
Bedminster, United States
18 h-index
31 publications
1.3K citations
Mentor Technologies
Tulsa, United States
17 h-index
72 publications
2.4K citations
1–8 of 302
75 publications · 3.8K citations
33
h-index
29 publications · 647 citations
16
h-index
20 publications · 1K citations
14
h-index
13 publications · 857 citations
12
h-index
JETTA · 13 publications · 228 citations
11
h-index
1–5