3D integration technology for set-top box application

Abstract

In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer. This flow needed to develop specific wafer level packaging technologies such as: (1) Top chip & bottom chip interconnections (2) High aspect ratio TSV included into the bottom wafer (3) Backside interconnections for subsequent packaging step (4) Temporary bonding and debonding of bottom wafer (5) Top chip stacking on bottom wafer. The complete process flow will be presented. Then, a technical focus will be done on the backside interconnections step. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed.