Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of ≪100≫ or ≪110≫ oriented FDSOI cMOSFETs for the 32nm Node

Abstract

For the first time, we integrated 1.9GPa eXtra-strained silicon on insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and width (W) down to 25nm. Due to the high stress levels, significant I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> -I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> improvements were obtained not only for nMOS but also for pMOS. We compared those results with the performance of devices strained by Contact Etch Stop Layer (CESL), for different device orientations (<110> or <100>) and feature sizes (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , W). We demonstrate that, similarly to XsSOI, a single tensile CESL can improve both n and pMOS performance, leading to I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,n</sub> =700 muA/mum and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,p</sub> =430 μA/μm at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =140 pA/μm, this for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> <35nm, W=50nm and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1V along the <100> direction.