C. Aulnette

Engineering strained silicon on insulator wafers with the Smart CutTM technology

B. Ghyselen, Jean‐Michel Hartmann, T. Ernst et al. · Solid-State Electronics · 2004 · 114 citations

Insulator Wafers, Semiconductor Technology, Electrical Engineering +8

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

A. Khakifirooz, Kangguo Cheng, Toshiharu Nagumo et al. · 2012 · 36 citations

Semiconductor Technology, Electrical Engineering, Engineering +14

Highly-Strained Silicon-On-Insulator Development

T. Akatsu, Jean‐Michel Hartmann, C. Aulnette et al. · ECS Transactions · 2006 · 11 citations

Materials Engineering, Semiconductor Technology, Electrical Engineering +14

Ultra-Thin Film SOI/BOX Substrate Development, Its Application and Readiness

W. Schwarzenbach, Xavier Cauchy, Olivier Bonnin et al. · ECS Transactions · 2011 · 11 citations

Engineering, Silicon On Insulator, Wafer Scale Processing +16

Stress Metrology : The challenge for the next generation of engineered wafers

Antoine Tiberj, Vincent Paillard, C. Aulnette et al. · MRS Proceedings · 2004 · 10 citations · Full text

Materials Science, Next Generation, Engineering +11