Faster defect localization in nanometer technology based on defective cell diagnosis

Abstract

In this paper we present practical techniques that enable diagnosis of defective library cells in a failing die. Our technique can handle large industrial designs and practical situations like compressed test patterns with multiple exercising conditions per pattern and sequence dependent defects. Being able to accurately differentiate between cell-internal and interconnect defects leads to a faster root cause failure analysis at a reduced cost. This capability was applied on an AMD graphics chip using 90nm at TSMC. In all of the failing dies that underwent physical failure analysis, the defective library cell identified by diagnosis was verified to be correct by failure analysis. Currently this capability is successfully used to diagnose another design using TSMC’s 65nm technology.