L.M. Huisman

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

T. Bartenstein, D. Heaberlin, L.M. Huisman et al. · 2002 · 206 citations

Engineering, Electronic Design Automation, Verification +24

Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT)

L.M. Huisman · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 97 citations

Engineering, Hardware Verification Language, Verification +24

A small test generator for large designs

Sandip Kundu, L.M. Huisman, I. Nair et al. · 1992 · 57 citations

Engineering, Computer Architecture, Test Data Generation +25

Data mining integrated circuit fails with fail commonalities

L.M. Huisman, Maroun Kassab, L. Pastel · 2005 · 54 citations

Engineering, Diagnosis, Fail Data +18

SLS-a fast switch-level simulator (for MOS)

Z. Barzilai, D.K. Beece, L.M. Huisman et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988 · 43 citations

Engineering, Hardware Verification Language, Computer Architecture +17