IEEE Transactions on Nuclear Science · 2012 · 17 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated Circuit DesignIntegrated Circuit DesignLow-power Digital Circuit DesignPhysical DesignCmos Digital Circuit DesignCmos ScalingFlip-flop DesignHardnessHysteresisPerformance OverheadPerformance Overhead AnalysisRadiation-hard Electronics
A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14× and 3× improvements in the alpha and neutron SER, respectively, compared with a standard DFF.
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