S.V. Walstra

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz et al. · 2004 · 153 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra et al. · IEEE Journal of Solid-State Circuits · 2004 · 111 citations

Low-power Electronics, Electrical Engineering, Engineering +12

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra et al. · 2004 · 67 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Circuit-level modeling of soft errors in integrated circuits

S.V. Walstra, Changhong Dai · IEEE Transactions on Device and Materials Reliability · 2005 · 64 citations

Electrical Engineering, Reliability Engineering, Analytical Soft-error Rate +15

Thin oxide thickness extrapolation from capacitance-voltage measurements

S.V. Walstra, Chih‐Tang Sah · IEEE Transactions on Electron Devices · 1997 · 42 citations

Device Modeling, Electrical Engineering, Engineering +13