Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

Abstract

We measured neutron soft error rate (SER) of hardened and standard latches in a 90 nm dual-Vt CMOS process. The hardened latch demonstrated over 10/spl times/ lower SER at no speed degradation. Energy penalty can be minimal for standard-latch transistor sizes at least twice the minimum size. We analyzed the effects of recovery time and leakage on the SER robustness.