K. Soumyanath

A sub-130-nm conditional keeper technique

Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath et al. · IEEE Journal of Solid-State Circuits · 2002 · 197 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

Erkan Alpman, Hasnain Lakdawala, L.R. Carley et al. · 2009 · 127 citations

Electrical Engineering, Engineering, Data Converter +11

Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 μ

Tanay Karnik, B. Bloechel, K. Soumyanath et al. · 2002 · 120 citations

Engineering, Cosmic Neutrino Background, Neutron Beam +17

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

Jeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas et al. · IEEE Journal of Solid-State Circuits · 2009 · 113 citations

Electrical Engineering, Engineering, High-frequency Device +12

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra et al. · IEEE Journal of Solid-State Circuits · 2004 · 111 citations

Low-power Electronics, Electrical Engineering, Engineering +12