Ram Krishnamurthy - Concepedia

Author

Ram Krishnamurthy

Also Known As

Charlotte Frenkel, Krishnamurthy, Ram, Krishnamurthy, Ram K, R Krishnamurthy, R. Krishnamurthy, R.K. Krishnamurthy, Ram K Krishnamurthy, Ram K. Krishnamurthy, Ram Krishnamurthy, Ram Kumar Krishnamurthy

214

Publications

4.8K

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Purdue University West Lafayette

About

Ram Krishnamurthy is an author at Intel (United States) specializing in computer engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	38	86	4.3K
2	Computer Engineering	38	85	4.3K
3	Education	4	4	182
4	Social Sciences	3	3	287
5	Applied Physics	3	3	224

Ram Krishnamurthy

Publications

4.4K

Citations

H-Index

Page 1

	Year	Citations
Near-threshold voltage (NTV) design Himanshu Kaul, Mark Anders, Steven Hsu, Low-power ElectronicsEnergy ConsumptionElectrical EngineeringEngineeringVlsi Design	2012	240
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS Sanu Mathew, Sudhir Satpathy, Mark Anders, Hardware SecurityLow-power ElectronicsElectrical EngineeringUnclonable Function CircuitUnclonable Function	2014	237
A sub-130-nm conditional keeper technique Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, IEEE Journal of Solid-State Circuits Hardware SecurityLow-power ElectronicsElectrical EngineeringStatistical Signal ProcessingEngineering	2002	197
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, IEEE Journal of Solid-State Circuits Flow ControlEngineeringNeural Networks (Machine Learning)Computer Architecture1M-synapse Chip	2018	197
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors Sanu Mathew, Suresh Srinivasan, Mark Anders, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignComputer Engineering	2012	188
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS Sanu Mathew, Sudhir Satpathy, Vikram Suresh, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureMv–1.1 VIntegrated Circuits	2015	137
53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignNm CmosComputer ArchitectureGbps Native	2011	137
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS Sudhir Satpathy, Sanu Mathew, Vikram Suresh, IEEE Journal of Solid-State Circuits Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringVlsi Design	2017	112
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, 2022 IEEE International Solid- State Circuits Conference (ISSCC) Convolutional Neural NetworkEngineeringComputer ArchitectureMulti-channel Memory ArchitectureHigh-performance Architecture	2022	100
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS Sudhir Satpathy, Sanu Mathew, Raghavan Kumar, IEEE Journal of Solid-State Circuits Hardware SecurityLow-power ElectronicsElectrical EngineeringEs Array SegregationEngineering	2019	98

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