Sudhir Satpathy

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders et al. · 2014 · 237 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Sanu Mathew, Suresh Srinivasan, Mark Anders et al. · IEEE Journal of Solid-State Circuits · 2012 · 188 citations

Low-power Electronics, Electrical Engineering, Engineering +10

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh et al. · IEEE Journal of Solid-State Circuits · 2015 · 137 citations

Engineering, Vlsi Design, Computer Architecture +19

Catnap

Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy et al. · 2013 · 136 citations

Hardware Security, Cluster Computing, Power-aware Computing +12

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

Sudhir Satpathy, Sanu Mathew, Vikram Suresh et al. · IEEE Journal of Solid-State Circuits · 2017 · 112 citations

Low-power Electronics, Hardware Security, Electrical Engineering +13