Raghavan Kumar - Concepedia

Author

Raghavan Kumar

Intel (United States)ORCID

Also Known As

Kumar, R.Satish, Kumar, Raghavan, R. Kumar, R.S. Vinod Kumar, Raghavan Kumar, Reddi Satish Kumar

Publications

1.4K

Citations

H-Index

Concepts

All Affiliations

Intel (United States)University of Massachusetts Amherst University of Passau

About

Raghavan Kumar is an author at Intel (United States) specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	24	1.1K
2	Computer Engineering	17	22	956
3	Computer Science	11	12	614
4	Social Sciences	2	2	228
5	Civil Engineering	1	1	101

Raghavan Kumar

Publications

1.2K

Citations

H-Index

Page 1

	Year	Citations
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, IEEE Journal of Solid-State Circuits Flow ControlEngineeringNeural Networks (Machine Learning)Computer Architecture1M-synapse Chip	2018	197
On design of a highly secure PUF based on non-linear current mirrors Raghavan Kumar, Wayne Burleson Hardware SecuritySecure PufElectrical EngineeringUnclonable FunctionsEngineering	2014	113
Passive Control of Vortex-Induced Vibrations: An Overview Raghavan Kumar, Chan‐Hyun Sohn, Bangalore Gowda Recent Patents on Mechanical Engineering AeroacousticsEngineeringFluid MechanicsMechanical EngineeringMarine Engineering	2008	101
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS Sudhir Satpathy, Sanu Mathew, Raghavan Kumar, IEEE Journal of Solid-State Circuits Hardware SecurityLow-power ElectronicsElectrical EngineeringEs Array SegregationEngineering	2019	98
22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications B. Sell, B. Bigwood, Soonwoo Cha, Low-power ElectronicsElectrical EngineeringRf ApplicationsEngineeringHigh-speed Electronics	2017	86
Active and Passive Side-Channel Attacks on Delay Based PUF Designs. Georg T. Becker, Raghavan Kumar IACR Cryptology ePrint Archive	2014	73
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware Raghavan Kumar, Philipp Jovanovic, Wayne Burleson, Hardware SecurityHardware TrojanStealthy Hardware TrojansEngineeringInformation Security	2014	69
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, EngineeringMachine LearningAdvanced ComputingSmart Web SearchComputer Architecture	2019	56
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS Phil Knag, Gregory K. Chen, H. Ekin Sumbul, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureBnn ChipIntegrated Circuits	2020	38
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, EngineeringMachine LearningNeural Network1M-synapse SnnSparse Weights	2018	31

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