Tanay Karnik - Concepedia

Author

Tanay Karnik

Intel (United States)ORCID

Also Known As

Karnik, T., T. Karnik, Tanay Karnik

162

Publications

8.1K

Citations

H-Index

148

Concepts

All Affiliations

Intel (United States)Intel (United Kingdom)Northwestern University

About

Tanay Karnik is an author at Intel (United States) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	44	77	7.9K
2	Natural Sciences	2	2	117
3	Social Sciences	2	2	226
4	Education	1	1	36
5	Medicine	1	1	337

Tanay Karnik

Publications

7.9K

Citations

H-Index

Page 1

	Year	Citations
Parameter variations and impact on circuits and microarchitecture Shekhar Borkar, Tanay Karnik, S. Narendra, Hardware SecurityLow-power ElectronicsElectrical EngineeringPhysical Design (Electronics)Engineering	2003	1.4K
Area-efficient linear regulator with ultra-fast load regulation P. Hazucha, Tanay Karnik, B. Bloechel, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignPower Ic	2005	547
Characterization of soft errors caused by single event upsets in CMOS processes Tanay Karnik, P. Hazucha IEEE Transactions on Dependable and Secure Computing EngineeringVlsi DesignComputer ArchitectureProcess SafetyHardware Security	2004	535
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance Keith Bowman, James Tschanz, Nam Sung Kim, IEEE Journal of Solid-State Circuits Equal ThroughputEngineeringVlsi DesignDatapath MetastabilityArtificial Immune System	2009	337
Review of On-Chip Inductor Structures With Magnetic Films Donald S. Gardner, G. Schrom, Fabrice Paillet, IEEE Transactions on Magnetics Magnetic PropertiesEngineeringMagnetic ResonanceIntegrated CircuitsMagnetic Materials	2009	328
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package P. Hazucha, G. Schrom, Jaehong Hahn, IEEE Journal of Solid-State Circuits Low-power ElectronicsPmos TransistorsElectrical Engineering233-Mhz 80Engineering	2005	301
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance Keith Bowman, James Tschanz, Shih‐Lien L. Lu, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignMicroprocessor CoreComputer ArchitectureIntegrated Circuits	2010	259
Design and reliability challenges in nanometer technologies Shekhar Borkar, Tanay Karnik, Vivek De EngineeringVlsi DesignComputer ArchitectureNanoelectronicsCmos Technology Scaling	2004	233
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging James Tschanz, Nam Sung Kim, Saurabh Dighe, EngineeringVlsi DesignComputer ArchitectureBody BiasHardware Security	2007	220
Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation P. Hazucha, Tanay Karnik, J. Maiz, Low-power ElectronicsElectrical EngineeringEngineeringNuclear PhysicsVlsi Design	2004	153

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