Characterization of soft errors caused by single event upsets in CMOS processes

TLDR

Radiation‑induced single event upsets threaten memory and logic design in high‑performance microprocessors beyond 90 nm, and the soft‑error rate must be added to the traditional power‑performance‑area trade‑offs. The study aims to analyze how radiation particle interactions in silicon generate charge‑collection soft errors that affect VLSI circuits and to assess their impact on system reliability, outlining future research directions. The authors accelerated SER measurement with a high‑intensity neutron beam, characterized SERs in sequential logic cells, and examined technology‑scaling trends.

Abstract

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.