Area-efficient linear regulator with ultra-fast load regulation

TLDR

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. The regulator uses a 1.2‑V input, 0.9‑V output, a 0.6‑nF on‑chip decoupling capacitor, and a PMOS pull‑up transistor, achieving a 90‑mV peak‑to‑peak output droop for a 100‑mA load step, a 0.008 mm² area, a 0.2‑V minimum dropout, and a 0.090 mm² capacitor area. Ultra‑fast single‑stage load regulation achieves a 0.54‑ns response time at 94 % current efficiency, while the PMOS pull‑up design yields a 0.008 mm² area and 0.2‑V minimum dropout for 100 mA output.

Abstract

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.