J. Maiz

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S.A. Hareland, Kedong Zhang et al. · 2004 · 242 citations

Hardware Security, Multi-bit Error Events, Engineering +14

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

N. Seifert, P. Slankard, Martin Kirsch et al. · 2006 · 202 citations

Hardware Security, Electrical Engineering, Engineering +11

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz et al. · 2004 · 153 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Influence of phonon, geometry, impurity, and grain size on Copper line resistivity

John J. Plombon, E. Andideh, Valery M. Dubin et al. · Applied Physics Letters · 2006 · 150 citations

Engineering, Submicron Copper Lines, Electron Diffraction +19