A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi, +50

Nm Logic TechnologyEngineeringVlsi DesignComputer ArchitectureHigh Volume +16

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S.A. Hareland, Kedong Zhang, +1

Hardware SecurityMulti-bit Error EventsEngineeringHardware ReliabilityError Control Technique +12

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

N. Seifert, P. Slankard, Martin Kirsch, +7

Hardware SecurityElectrical EngineeringEngineeringVlsi DesignComprehensive Summary +9

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz, +7

Low-power ElectronicsElectrical EngineeringEngineeringNuclear PhysicsVlsi Design +9

Influence of phonon, geometry, impurity, and grain size on Copper line resistivity

John J. Plombon, E. Andideh, Valery M. Dubin, +1

Applied Physics Letters

EngineeringSubmicron Copper LinesElectron DiffractionGrain SizeNarrowest Line +17

Cross-sectional nanoindentation: a new technique for thin film interfacial adhesion characterization

J.M. Sánchez, Safaa El-Mansy, Benyuan Sun, +10

Acta Materialia

Materials ScienceEngineeringCross-sectional NanoindentationMicrofabricationAdhesive Material +6

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier, +19

Materials EngineeringNmos BtiElectrical EngineeringEngineeringHardware Reliability +11

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

S.A. Hareland, J. Maiz, M. Alavi, +3

Hardware SecurityElectrical EngineeringEngineeringVlsi DesignHardware Reliability +12

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra, +8

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignLocal Redundancy +10

Crystal plasticity in Cu damascene interconnect lines undergoing electromigration as revealed by synchrotron x-ray microdiffraction

Arief Suriadi Budiman, William D. Nix, Nobumichi Tamura, +5

Applied Physics Letters

Point DefectsEngineeringSevere Plastic DeformationSynchrotron X-ray MicrodiffractionInterconnect (Integrated Circuits) +17